Designed for applications where high data sampling is required, the IC-ADC-FMCPa is a VITA 57.4 FPGA Mezzanine Card (FMC). It offers a flexible connectivity with our FPGA 3U and 6U Front End Processing boards running our Signal Processing Reference Design (including signal acquisition, Processing DMA Engine, data storage, signal generation,…) thus allowing customers to streamline development of high performance signal acquisition systems by concentrating their efforts on their most critical tasks.

The IC-ADC-FMCPa is available in three sample rate configurations : 2 and 2.5 Gsps (3 Gsps as an option).

  • FMC – VITA57.4 HSPC Compliant
  • 4 Channels 14-bit, 2 or 2.5/2.6 Gsps A/D
  • JESD204B Interfaces
  • SSMC Connectors
  • Conduction-cooled compliant

  • Two Analog Devices ADCs with 14-bit resolution
  • Sampling rate up to 2.6 Gsps (option 3Gsps)
  • 4 channels with SSMC connectors (*)
  • Input impedance 50 Ohm AC coupled
  • Full scale ampliture 1.5 V peak-peak (soft. con?g.)
  • Analog input bandwidth (-3dB) 10MHz – 4GHz

  • Sampling Clock (CKI):
  • SSMC (*) connector, 50 Ohm, AC coupled
  • Input level
    • Sine wave: 0 to +10dB
  • Frequency range: CKI from 1900 MHz to 2600 MHz

  • ADC Output: CML – 16 lines 12.5Gbps, at 2.5 GSPS, DDC bypassed
  • (options: 13Gbps, at 2.6 GSPS, DDC bypassed 15Gbps, at 3 GSPS, DDC bypassed)