4DSP Announces Recent and Upcoming Improvements to its StellarIP FPGA Firmware Development Tool

Posted: November 17, 2014

4DSP is proud to announce a number of improvements to StellarIP that expand its feature set while also making it more user-friendly. StellarIP is an essential productivity tool that simplifies FPGA firmware design by relying on proven IP cores. 4DSP reference designs leverage the extensive library of firmware at the heart of StellarIP to ensure that customers are up and running as soon as they receive their hardware. It features a graphical schematics entry tool to further simplify the design process. StellarIP makes the integration of new cores easier and enables them to be reused across multiple designs. It also automates the creation and compilation of Xilinx ISE and Vivado projects and simulation scripts.

Foremost among the enhancements delivered in 2014 are significant improvements to the graphical interface which simplify editing, as well as greater design integrity protection which helps to minimize mistakes and save time. Additionally, StellarIP now supports Microsoft Windows 8.1, and it has the ability to automatically download updates, enabling 4DSP to easily deliver the latest features, improvements, and bug fixes. In anticipation of Xilinx’s plan to switch to Vivado for all of its future FPGA products, StellarIP now also features Vivado support. An exciting benefit of this is the ability for users to regenerate old ISE designs for Vivado for compatible FPGA types. Vivado is Xilinx’s future, and 4DSP is ready for it.

“The key aspects of these extensive StellarIP enhancements are better design and library integrity which support a more intuitive approach to high-level firmware design,” said 4DSP software engineer Remco Boom. “StellarIP offers a level of flexibility that allows FPGA firmware designers to quickly achieve their goals while avoiding unnecessary mistakes.” Knowledge of an HDL language is not required for using StellarIP. This provides software engineers with the ability to create new FPGA designs by relying on existing IP and to extend their domain of influence to the entire system.

Looking ahead, the development roadmap for StellarIP promises further improvements. “We plan to streamline the process of firmware updates, add support for VHDL generics, and implement an automated assistant to guide users in creation of stars (the StellarIP term for IP blocks),” said 4DSP software engineering manager Arnaud Maye. “We are working constantly to improve the functionality and usability of StellarIP to help our customers easily and effectively implement their designs.” StellarIP has enabled 4DSP engineers to increase their productivity tremendously as they generate new FPGA designs for different platforms. What used to take weeks is now a matter of days. This is reflected by the hundreds of reference designs that 4DSP has made available to its customer base over the past few years.

Selected Updates and Improvements:

  • Improved graphical interface
  • Improved library and design integrity protection
  • Library merging
  • Local library support
  • Search in library view to speed up library editing
  • More pre-generate checks and better error and warning messages
  • Improved log output window (including Xilinx shell outputs redirected to StellarIP)
  • File type registration and double click support from Windows Explorer
  • Text file editor
  • More custom configuration settings
  • Automatic version updates
  • Help files
  • Xilinx ISE and Vivado support
  • Windows 8.1 support

StellarIP is included for free as part of 4DSP’s Board Support Package (BSP). It can be used with 4DSP hardware or any third-party FPGA platform under licensing. More information about this tool can be found here: