Hardware

IC-FEP-VPX6b – Virtex®-7 & QorIQTM 6U VPX processing unit

Virtex®-7 & QorIQTM 6U VPX processing unit

The IC-FEP-VPX6b is controlled by a QorIQ T1042 quadcore supporting four integrated 64-bit e5500 Power Architecture ® processor cores with high-performance data path acceleration architecture (DPAA) and network peripheral interfaces required for demanding processing application.

(Option: T2081 with four dual threaded e6500 64-bit cores implementing Altivec technology; up to 4GB DDR3)

The QorIQ provides the usual external interfaces: Ethernet, Serial and USB ports. Moreover, one eUSB slot allows to plug an optional SSD module.

The PCIe advanced switch allows versatile coupling between the processor, the FPGAs and the fabric links of P1 VPX connector. (Non transparent configuration possible for VPX fabric link).

Other Fabric Links of the VPX backplane are directly connected to the FPGAs GTH transceivers. Moreover, the two FPGAs are directly interconnected via 8 GTH lanes and 35 LVDS signals.

Main Features

Processing Units

  • One QorIQ processor T1042, e5500 quad core with:
    • 2 GB of DDR3L SDRAM with ECC (up to 4GB)
    • 3 * 1GB Mirrorbit SPI Flashes (Boot, BackUp & User, option: 2GB possible)
    • 32GB (MLC) or 16GB (SLC) Nand flash (user)
    • optional Nand Solid-state Disk (eUSB module)
  • two Xilinx Virtex-7 XC7VX690T, both offering:
    • two banks of DDR3 : 64-bit wide/2GB each
    • two banks of SRAM DDRII+: 18-bit wide/72 Mbits (up to 144Mb)
  • SPI mirror flash memories (VX330T or VX485T possible with restriction) the two FPGA are interconnected through:
    • 8 * GTH lanes
    • 35 * LVDS

VPX Interfaces 

  • 4 * PCIe x4 port (from PCIe switch)
  • GTH ports (4 * GTH x4 from each FPGA)
  • General purpose IOs
    • 2*16LVDS (16 from each FPGA)
    • 2*16 differential pairs (16 from each optional FMC IOs connector)
    • 3 * QorIQ Serdes (1*PCie x1 & 2 Sata or 2*PCie x1 & 1 Sata)
  • 4 * Ethernet ports (2 * 1000BT & 2 * 1000BX – from switch)
  • 1 * RS485/RS232 port
  • 2 * USB 2.0 ports
  • PIC μ-controller for System Management (per VITA 46.11))

FMC interfaces (for each site, from FPGAs)

  • 80 LVDS
  • 4 reference clocks
  • 2 * GTH x4 links
  • optional connector for IOs report to the backplane

Front panel interfaces
1 * USB 2.0, 1 * Ethernet 1000BT, 1 * console port and leds

The IC-FEP-VPX6b is a VPX 6U / 4HP 1” board compliant with 6U module definitions of the VITA 46.0 standard. It is available in air-cooled and conduction-cooled grades.

ds_popup_1